1. Field of the Invention
The present invention relates generally to a disc drive controller which controls the input and output of digital data to and from an optical or magnetic disc drive. The controller determines whether an error has occurred in the input and output of the data to the disc drive according to detection of data encoded with a Run Length Limited code and a synchronized pattern.
2. Description of the Related Art
FIG. 1 shows a conventional data processing device in which an optical disc is used as the main source for storing data. The controller includes a disc controller 110, a micro processing unit (hereinafter referred to as MPU) 113, a dynamic random access memory (hereinafter referred to as DRAM) 114 as an external memory, an optical disc 118 and a disc drive 200. The disc drive 200 responds to the disc controller's data input and output (I/O) instructions by performing operations such as the reading and writing of data respectively to and from the disc 118, according to a particular modulated digital code.
The job of a controller is to control and handle the bus access for the I/O devices coupled to the computer 119. When a program wants data from an I/O device, it causes a demand to be given to the disc controller, which then issues seek and other commands to the drive. When a particular track and sector on the storage medium has been located by the drive, the drive begins outputting the data as a serial bit stream to the controller. It is the job of the controller to break the bit stream up into words, and write each word into to a particular memory, as it is assembled.
FIG. 6 is illustrative of a sector of formatted binary data, i.e., the smallest contiguous binary sequence used in the transfer of data to and from a storage medium, such as the disc 118. A sector 80 includes a fixed length address field 81 and a fixed length data field 82. A variable frequency oscillator pattern (hereinafter referred to as VFO) 83 and a SYNC pattern 84 are stored in the data field 82. Following the SYNC pattern 84, a run length limited code data (hereinafter referred to as RLL) 85 is stored in the data field 82. This RLL code represents the limited number of continuous binary zeros (i.e., "0's") that are disposed between binary ones (i.e., "1's"). Specifically, RLL encoding maps the maximum and minimum spaces occurring between consecutive transitions in a binary waveform to maximum and minimum run lengths of 0's occurring between two consecutive 1's in the respective encoded binary sequence.
The RLL encoded data 85 in FIG. 6 is formed with fifteen bytes. Subsequent in placement to the RLL encoded data 85, a RESYNC pattern 86 is stored in the data field 82. RLL encoded data 85 and RESYNC pattern 86 are continuously and alternatingly stored in the data field 82. A post amble pattern (hereinafter referred to as PA) 87 is stored at the very end of the data field.
As FIG. 1 further illustrates, the design of a conventional controller 110 includes a buffering circuit 111 and a formatter 112. These components are usually found integrated on a single chip, with the buffering circuit 111 communicatively coupled to the computer 119, MPU 113 and DRAM 114. Such a design allows the buffering circuit 111 to regulate the input and output of digital data to various computer peripherals.
A single control signal, transmitted from the MPU 113 to the buffering circuit 111, effects the parallel transfer of parallel binary data between the DRAM and computer 119. Such binary data is usually transferred in 512 byte segments containing single byte units. Another operation performed by buffering circuit 111 based on a control signal is the parallel transfer of single byte units of binary data between the DRAM 114 and the formatter 112. When the buffering circuit 111 transfers data from the DRAM 114 to the formatter 112, the buffering circuit 111 computes an error correction code in order to correct for errors existing in data with respect to every byte transferred. The computed error correction code is stored in a memory (not shown) disposed in the buffering circuit 111. After the operation for transferring the 512 byte data is completed, the buffering circuit 111 transfers the computed error correction code by a single byte unit.
This data is then stored in DRAM 114, under the control of the buffering circuit 111, at a memory location corresponding to the particular sector of the disc 118 where the data was stored. Buffering circuit 111 performs this operation while at the same time it incorporates error detection circuitry to detect errors occasioned which might have occurred during the data transfer. This correction routine is usually based upon the error correction code incorporated with the transferred data. After the data correction operation, the buffering circuit 111 removes the incorporated error correction code from the read data, and transfers the remaining data to the DRAM 114 in single byte units.
The formatter 112 usually includes a serializer 115, a deserializer 116 and a modulator-demodulator 117. The serializer 115 converts a single byte of data, transferred in parallel under control of the buffering circuit 111, into serial data. The serializer 115 outputs the converted serial data to the modulator-demodulator 117 where the data is then modulated into RLL encoded data. Next, the modulator-demodulator 117 adds the VFO pattern, SYNC pattern and RESYNC pattern, and a post amble pattern to the very end of the RLL encoded data. The modulator-demodulator 117 then outputs the resultant data segment to the optical disc 118 as write-in data (WDATA).
On the other hand, during a reading operation, data is read from the disc 188 as read-out data (RDATA) and transferred by means of the drive 200 to the modulator-demodulator 117. The modulator-demodulator 117 detects and removes any encoded synchronized and post amble patterns present in data RDATA. Following that, the modulator-demodulator 117 demodulates the RLL encoded data into binary serial data, which is output to the deserializer 116. The serial data is then converted by deserializer 116 to parallel data which is output under the control of the buffering circuit 111.
Error correction protocol is a crucial facet of efficient data transfer. Conventional error correction circuitry is typically integrated into the disc controller 110 and operates in the following manner.
A first sample of error encoded read-out RDATA is read from the disc 118 by disc drive 100 under the control of disc controller 110. This first sample of data is transferred to the formatter 112 where the sample's RLL code is demodulated by demodulator 117 and deserialized by deserializer 116 into parallel data. From the formatter 112, this first sample of parallel data, having an error code incorporated therein, is transferred by the buffering circuit to the DRAM 114 for storage. A part of the data stored in the DRAM 114 is then intentionally rewritten. The error encoded binary data is then output to the modulator-demodulator 117, where it is modulated into a respective RLL encoded data. The modulated data is output to the driver 200, and is written in the disc 118 by means of the driver 200. Then, the data is read out from the disc 118 and demodulated by means of the modulator-demodulator 117. The operation for correcting the errors is applied on the read-out data by means of the buffering circuit 111, similar to the normal operation. Only the regular data portion in the corrected data is loaded into the DRAM 114. This loaded data is compared with the data previously stored in the DRAM 114. The testing operation is carried out by finding the position where the errors were stored and by finding how the errors occurred, through the result of this comparison.
However, in the controller 110, the modulator-demodulator 117 removes the annexed synchronized patterns in the read-out data RDATA transmitted from the disc 118. The modulator-demodulator 117 demodulates only the RLL code data that corresponds to the remaining data. The demodulated data is outputted to the buffering circuit 111. Unfortunately, when the data in the disc 118 is not accurately read out, perhaps due to an error spot existing on the disc 118 or in the controller itself, a testing routine for finding out whether the error occurred in the controller 110 or the disc 118 has not as yet been incorporated into the controller.
This is particularly disadvantageous since the modulator-demodulator is responsible for modulating the write-in data WDATA according to various codes and a synchronized pattern. Therefore, when the failure exists in the modulation-demodulation component 117 of the controller 110, it is as yet been impossible to detect.